As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems often use memories to store data, either temporarily in volatile memory or in a quasi-permanent basis in non-volatile memory. A type of memory often used is dynamic random access memory (DRAM). DRAM includes a number of memory cells each configured to store one bit of data. One crucial timing parameter of a DRAM is the write recovery parameter, which defines a minimum time required to ensure that a DRAM cell has been written to its full charge. As DRAM technology has scaled to smaller and smaller physical sizes, suppliers of DRAMs have indicated a desire to increase the write recovery parameters of their DRAMs, and have pursued relaxation of the write recovery parameter with the Joint Electron Device Engineering Council (JEDEC), the computing industry's memory standards-setting organization. Without this timing relaxation, the DRAM bit error rate due to write failures may become so high as to make DRAM chips non-manufacturable at an acceptable yield. Such increases in the write recovery parameters and other timing parameters of DRAM may significantly reduce bandwidth of memory devices.
In addition, in many DRAMs, the write time of a memory cell may increase as the ambient temperature of the memory cell falls, further degrading memory performance as temperature decreases. In fact, many in the relevant industry have proposed that for future memory implementations, DRAM timing parameters such as the write recovery parameter be a function of operating temperature. For example, in future DRAM devices, a write recovery parameter may have a value of 60 nanoseconds for temperatures below 45 degrees Celsius and a value of 30 nanoseconds for temperatures above 45 degrees Celsius. Such DRAM devices may also be enabled such that a memory controller of a DRAM device may be notified of such changes in temperature and modify timing parameters in accordance with such temperature.
Because an increase in write recovery time increases overall DRAM write latency and read-after-write latency to the same DRAM rank, maximum memory bandwidth may decrease due to a drop in temperature. Thus, with the industry-proposed changes to move towards temperature-based timing parameters, when a temperature falls below a certain level, write latency may triple and write bandwidth would fall by up to two-thirds when writes are issued to the same DRAM rank and bank. Another disadvantage is that variable memory latency which varies with temperature may create undesirable effects in application programs which are sensitive to timing variation, either with the same rank or different ranks.